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STV7699
PLASMA DISPLAY PANEL DATA DRIVER
. . . . . . . . .
PRODUCT PREVIEW
64 OUTPUTS PLASMA DISPLAY DRIVER 170V ABSOLUTE MAXIMUM SUPPLY 5V SUPPLY FOR LOGIC 50/40mA SOURCE / SINK OUTPUT 60/60mA SOURCE / SINK OUTPUT DIODE 64-BIT SHIFT REGISTER (20MHz) BLK, POLARITY AND HIZ CONTROL BCD TECHNOLOGY DIE or 100-PIN PQFP PACKAGE
PQFP100 (14 x 20 x 2.80mm) (Full Plastic Quad Flat Pack) ORDER CODE : STV7699
DESCRIPTION The STV7699 is a Plasma Display Panel (PDP) data driver implemented in ST's proprietary BCD technology. Using a 4-bit wide cascadable shift register, it drives 64 high current & high voltage outputs. By serialy connecting several STV7699, any horizontal pixel definition can be performed. The 20MHz shift clock gives an equivalent 80MHz shift register. The STV7699 is supplied with a separated 170V power output supply and a 5V logic supply. PIN CONNECTIONS
OUT24 OUT23 OUT22 OUT21 OUT20 OUT19 OUT18 OUT17 OUT16 OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7
All command inputs are CMOS compatible. The STV7699 package is a 100-pin PQFP. It is also available as die.
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1 2
VSSP
VSSP
VSSP
VPP
VPP
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
OUT25 OUT26 OUT27 OUT28 VSSP OUT29 OUT30 OUT31 OUT32 VSSP VSSSUB OUT33 OUT34 OUT35 OUT36 VSSP OUT37 OUT38 OUT39 OUT40
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
1
VPP
100 99 98 97 96 95 94
VCC A1 A2 A3 A4 CLK STB VSSLOG VSSLOG VSSLOG VSSLOG F/R BLK POL HIZ B4 B3 B2 B1 VSSSUB
STV7699
PQFP100 (Top View)
93 92 91 90 89 88 87 86 85 84 83 82 81
January 1999
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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7699-01.EPS
OUT41
OUT42
OUT43
OUT44
OUT45
OUT46
OUT47
OUT48
OUT49
OUT50
OUT51
OUT52
OUT53
OUT54
OUT55
OUT56
OUT57
OUT58
OUT59
OUT60
OUT61
OUT62
OUT63
OUT64
VSSP
VSSP
VSSP
VPP
VPP
VPP
STV7699
PIN ASSIGNMENT (PQFP100)
Pin Number 100 1 - 29 - 30 - 51 - 52 - 80 6 - 15 - 24 - 35 - 40 46 - 57 - 66 - 75 90 to 93 41 - 81 Symbol VCC VPP VSSP VSSLOG VSSSUB Type Supply Supply 5V Logic Supply High Voltage Supply of power outputs Function
Ground Ground of power outputs Ground Logic Ground Ground Substrate Ground Power Output
2 to 5 - 7 to 14 - 16 to 23 OUT1 to OUT 64 Output 25 to 28 - 31 to 34 - 36 to 39 42 to 45 - 47 to 50 - 53 to 56 58 to 65 - 67 to 74 - 76 to 79 95 CLK Input
Clock of data shift register Low to High transition makes the data enter into the shift register and available at the output stage and at the output of the shift register. Latch of data to outputs When the STB signal is set to low level, data are transferred into the latch stage. When STB is set at high level, data are held in the latch stage. Power Output Blanking Control Power Output Polarity Control Power Output High Impedance Control Selection of shift direction Shift register data input and output according to F/R value. When set to low, Ai = input and Bi = output.
7699-01.TBL 7699-02.TBL
94
STB
Input
88 87 86 89 96 to 99 82 to 85
BLK POL HIZ F/R A4 to A1 B1 to B4
Input Input Input Input Input Output
PIN ASSIGNMENT (Power Outputs)
Output N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin N 2 3 4 5 7 8 9 10 11 12 13 14 16 17 18 19 Output N 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin N 20 21 22 23 25 26 27 28 31 32 33 34 36 37 38 39 Output N 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin N 42 43 44 45 47 48 48 50 53 54 55 56 58 59 60 61 Output N 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin N 62 63 64 65 67 68 69 70 71 72 73 74 76 77 78 79
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STV7699
PAD DIMENSIONS (in m) The reference is the center of the die (x = 0, y = 0). LEFT SIDE from top to bottom
Name VPP OUT1 OUT2 OUT3 OUT4 VSSP OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 VSSP OUT13 OUT14 OUT15 OUT16 OUT17 OUT18 OUT19 OUT20 VSSP OUT21 OUT22 OUT23 OUT24 VPP Center : X Center : Y Size : x -1738.0 2867.5 90.0 -1738.0 2703.0 90.0 -1738.0 2570.5 90.0 -1738.0 2411.0 90.0 -1738.0 2228.5 90.0 -1738.0 2093.0 90.0 -1738.0 1952.0 90.0 -1738.0 1813.5 90.0 -1738.0 1631.0 90.0 -1738.0 1453.0 90.0 -1738.0 1235.5 90.0 -1738.0 1046.5 90.0 -1738.0 862.0 90.0 -1738.0 712.5 90.0 -1738.0 566.0 90.0 -1738.0 431.0 90.0 -1738.0 293.0 90.0 -1738.0 82.5 90.0 -1738.0 -109.5 90.0 -1738.0 -277.0 90.0 -1738.0 -471.0 90.0 -1738.0 -691.5 90.0 -1738.0 -822.5 90.0 -1738.0 -953.0 90.0 -1738.0 -1096.0 90.0 -1738.0 -1335.5 90.0 -1738.0 -1569.0 90.0 -1738.0 -1697.5 90.0 -1715.0 -2045.0 90.0 Size : y 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 200.0
Right SIDE from bottom to top
Name VPP OUT41 OUT42 OUT43 OUT44 VSSP OUT45 OUT46 OUT47 OUT48 OUT49 OUT50 OUT51 OUT52 VSSP OUT53 OUT54 OUT55 OUT56 OUT57 OUT58 OUT59 OUT60 VSSP OUT61 OUT62 OUT63 OUT64 VPP Center : X Center : Y Size : x 1600.5 -2087.0 90.0 1737.5 -1646.0 90.0 1737.5 -1507.0 90.0 1737.5 -1328.0 90.0 1737.5 -1096.0 90.0 1737.5 -953.0 90.0 1737.5 -822.5 90.0 1737.5 -691.5 90.0 1737.5 -471.0 90.0 1737.5 -277.0 90.0 1737.5 -109.5 90.0 1737.5 82.5 90.0 1737.5 293.0 90.0 1737.5 431.0 90.0 1737.5 566.0 90.0 1737.5 712.5 90.0 1737.5 862.0 90.0 1737.5 1046.5 90.0 1737.5 1235.5 90.0 1737.5 1453.0 90.0 1737.5 1631.0 90.0 1737.5 1813.5 90.0 1737.5 1952.0 90.0 1737.5 2093.0 90.0 1737.5 2228.5 90.0 1737.5 2411.0 90.0 1737.5 2570.5 90.0 1737.5 2703.0 90.0 1737.5 2873.5 90.0 Size : y 200.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0
BOTTOM SIDE from left to right
Name OUT25 OUT26 OUT27 OUT28 VSSP OUT29 OUT30 OUT31 OUT32 VSSP VSSSUB OUT33 OUT34 OUT35 OUT36 VSSP OUT37 OUT38 OUT39 OUT40 Center : X Center : Y Size : x -1443.5 -3077.0 75.0 -1249.0 -3077.0 75.0 -1049.5 -3077.0 75.0 -889.0 -3077.0 5.0 -753.0 -3077.0 75.0 -614.0 -3077.0 75.0 -467.5 -3077.0 75.0 -332.0 -3077.0 75.0 -186.5 -3077.0 75.0 -54.0 -3077.0 75.0 78.0 -3077.0 75.0 209.5 -3077.0 75.0 342.5 -3077.0 75.0 467.5 -3077.0 75.0 607.5 -3077.0 75.0 752.0 -3077.0 75.0 892.5 -3077.0 75.0 1045.5 -3077.0 75.0 1252.0 -3077.0 75.0 1433.5 -3077.0 75.0 Size : y 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0
TOP SIDE from right to left
Name VSSSUB B1 B2 B3 B4 HIZ POL BLK F/R VSSLOG VSSLOG STB CLK A4 A3 A2 A1 VCC Center : X Center : Y Size : x 1628.5 3073.5 75.0 1478.5 3073.5 75.0 1228.5 3077.0 75.0 978.5 3077.0 75.0 847.5 3077.0 75.0 716.5 3077.0 75.0 486.5 3077.0 75.0 355.5 3077.0 75.0 224.5 3077.0 75.0 31.0 3077.0 200.0 -354.5 3077.0 200.0 -582.0 3077.0 75.0 -713.0 3077.0 75.0 -844.0 3077.0 75.0 -975.0 3077.0 75.0 -1106.0 3077.0 75.0 -1471.5 3077.0 75.0 -1629.0 3077.0 75.0 Size : y 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 3/9
STV7699
BLOCK DIAGRAM
CLK 95 A1 99
P1
16-BIT SHIFT REGISTER
P61
89 F/R 82 B1
16-BIT SHIFT REGISTER A2 98
P2 P62
83 B2
16-BIT SHIFT REGISTER A3 97
P3 P63
84 B3
16-BIT SHIFT REGISTER A4 96
P1 P4 P64
85 B4
100
P4
P63 P64
STB 94
Q1 Q2
LATCH
Q63Q64
VCC VSSLOG Pins 90 to 93 VSSSUB Pins 41-81 VSSP Pins 6-15-24-35 40-46-57-66-75 VPP Pins 1-29-30 51-52-80
BLK 88
POL 87
HIZ 86
2 OUT1
79 OUT64
CIRCUIT DESCRIPTION The STV7699 contains all the logic and the power circuits necessary to drive the colums of a Plasma Display Panel (P.D.P.). Data are shifted at each low to high transition of the (CLK) shift clock. Data are input in a 4-bit wide data bus to A1 - A4 input (case of forward shift mode ; F/R = low). After 16 shifts, the first nibble is available at the serial outputs B1 - B4. These outputs can be used to cascade several drivers to performed any horizontal resolution. CLK, Ai and Bi inputs are Smith trigger inputs to improve the noise margin. The Forward/Reverse (F/R) input is used to select the direction of the shift register. The maximum frequency of the shift clock is 20MHz. All the output data are held and memorized into the latch stage when the Latch input (STB) is high. When it is at low level, data are transferred from the shift register to the latch and to the output power stage. Output state can be forced to high impedance by pulling low HIZ input. When BLK is Low, all the outputs are forced to low level or high level according to POL signal value. Output state copy data that was input, with the
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same polarity, when BLK, HIZ and POL are High. VSSLOG, VSSSUB and VSSP are not internally connected. VSSLOG and VSSSUB must be connected as close as possible to the logical reference ground of the application. Table 1 : Power Output Truth Table
Data STB POL BLK HIZ Driver Output x x x x L HIZ x x L x H L x x H L H H x H H H H Qn (1) L L H H H L H L H H H H Comments High impedance Forced to low Forced to high Latched data Copy data Copy data
Note 1 : Qn is the value memorised in the latch stage ; it is the value of the parallel shift register output stage after n Clock pulses.
A data loaded in the shift register is read on the output power stage without inversion of its polarity. Table 2 : Control Table
F/R L H Ai Input Output Bi Output Input Comments Forward shift Reverse shift
7699-02.EPS
STV7699
STV7699
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VIN VOUT VPOUT VPP IPOUT IDOUT Tjmax Toper Tstg Parameter Logic Supply Logic Input Voltage Logic Output Voltage Driver Output Voltage Driver Power Supply Driver Output Current (2) Diode Output Current (2) Junction Temperature Operating Temperature Storage Temperature Value -0.3, +7 -0.3, VCC + 0.3 -0.3, VCC + 0.3 -0.3, +170 -0.3, +170 60 +40/-50 +150 -20, +85 -50, +150 Unit V V V V V mA mA C C C
THERMAL DATA
Symbol Parameter Rth(j-a) Junction-ambient Thermal Resistance (1) Poper Operating Power Dissipation (Tamb = 25C) Tjoper Operating Junction Temperature (1) Max. Max. Max. Value 50 2 +125 Unit C/W W C
Notes : 1. For PQFP100 packaging. 2. Through all power outputs : with power dissipation lower or equal than Ptot and junction temperature lower or equal than Tjmax.
ELECTRICAL CHARACTERISTICS (VCC = 5V, VPP = 160V, VSSP = 0V, VSSLOG = 0V, VSSSUB = 0V, Tamb = 25C, fCLK = 20MHz, unless otherwise specified)
Symbol SUPPLY VCC ICCH ICCL VPP IPPH OUTPUT OUT1-OUT64 VPOUTH Power Output High Level VPOUTL VDOUTH VDOUTL IOUTHIZ Power Output Low Level IPOUTH = - 10mA, VPP = 65V IPOUTH = - 40mA, VPP = 65V IPOUTL = + 10mA IPOUTL = + 30mA IDOUTH = + 25mA (3)(4) IDOUTL = - 25mA (3)(4) 55 TBD 4 0.8 VCC 60 2 12 0.1 5 TBD 3 -3 10 0.3 0.2 VCC 1 -1 V V V V V V A V V V V A A Logic Supply Voltage Logic Supply Current Logic Supply Current fCLK = 20MHz Power Output Supply Voltage Power Output Supply Current (steady outputs) 4.5 5 12 5.5 100 TBD 160 100 V A mA V A Parameter Test Conditions Min. Typ. Max. Unit
Output Diode High Level Output Diode Low Level Output Stage Leakage Current on HIZ State SHIFT REGISTER OUTPUT (Ai or Bi according to F/R Status) VOH Logic Output High Level IOH = - 0.5mA VOL Logic Output Low Level IOL = + 0.5mA INPUT (CLK, STB, BLK, HIZ, Ai, Bi) VIH VIL IIH IIL Input High Level Input Low Level High Level Input Current Low Level Input Current
VIH = VCC VIL = 0V
Notes : 3. Compatible with power dissipation and Tjoper 125C. 4. See test diagram.
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7699-05.TBL
7699-04.TBL
7699-03.TBL
STV7699
AC TIMINGS REQUIREMENTS (VCC = 4.5V to 5.5V, Tamb = -20 to +85C, input signals max leading edge & trailing edge (tR, tF) = 10ns)
Symbol tCLK tWHCLK tWLCLK tSDAT tHDAT tDSTB tSTB tBLK tPOL tHIZ tSFR Data Clock Period Duration of clock (CLK) pulse at high level Duration of clock (CLK) pulse at low level Set-up Time of data input before clock (low to high) transition Hold Time of data input after clock (low to high) transition Minimum Delay to latch (STB) after clock (low to high) transition Latch (STB) Low Level Pulse Duration Blanking (BLK) Pulse Duration Polarity (POL) Pulse Duration High Impedance (HIZ) Pulse Duration Set-up Time of Forward /Reverse Signal before Clock (low to high) transition Parameter Min. 50 15 15 0 15 20 10 100 100 100 100 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns
7613-06.TBL 7613-07.TBL
AC TIMING CHARACTERISTICS (VCC = 5V, VPP = 65V, VSSP = 0V, VSSLOG = 0V, VSSSUB = 0V, Tamb = 25C, VILMax. = 0.2VCC, VIHMin. = 0.8VCC, VOH = 4.0V, VOL = 0.4V, CL = 10pF, unless otherwise specified)
Symbol tCLK tRDAT tFDAT tPHL1 tPLH1 tPHL2 tPLH2 tPHL3 tPLH3 tPHL4 tPLH4 tPHZ5 tPLZ5 tPZH5 tPZL5 tROUT tFOUT Data Clock Period Logical Data Output Rise Time Logical Data Output Fall Time Delay of logic data output (high to low transition) after clock (CLK) transition Delay of logic data output (low to high transition) after clock (CLK) transition Delay of power output change (high to low transition) after clock (CLK) transition Delay of power output change (low to high transition) after clock (CLK) transition Delay of power output change (high to low transition) after Latch (STB) transition Delay of power output change (low to high transition) after Latch (STB) transition Delay of power output change (high to low transition) to Blank (BLK) or Polarity (POL) transition Delay of power output change (low to high transition) to Blank (BLK) or Polarity (POL) transition Delay of power output change (high to Hi-Z transition) after high impedance (HIZ) (5) Delay of power output change (low to Hi-Z transition) after high impedance (HIZ) (5) Delay of power output change (Hi-Z to high transition) after high impedance (HIZ) (5) Delay of power output change (Hi-Z to low transition) after high impedance (HIZ) (5) Power Output Rise Time (6) Power Output Fall Time (6) Parameter Min. 50 Typ. Max. Unit TBD TBD 40 40 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 30 30 TBD TBD 120 120 110 110 100 100 100 100 100 100 150 150 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes : 5. See test diagram. 6. One output among 64, loading capacitor COUT = 50pF, other outputs at low level.
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STV7699
Figure 1 : AC Characteristics Waveform
tCLK tWHCLK tWLCLK "1" CLK 50% 50% tSDAT 50% "0" tHDAT "1" SIN 50% tPHL1 "1" 50% "0" tRDAT tSTB tDSTB STB 50% tSFR "1" F/R tPHL3 90% 10% tPLH3 tPOL "1" POL 50% tPLH4 90% OUTn tHIZ "1" HIZ tROUT 90% 10% 90% 10% tFOUT 50% tPHZ5 90% 10% tPLZ5 50% "0" tPZH5 90% 10% tPZL5
7699-03.EPS
50% "0"
tFDAT SOUT 90% 10%
tPLH1 "1" 50% "0"
50% "0" tPHL2 "1" 90% 10% 90% 10% "0" tPLH2
OUTn
50% "0" tPHL4 "1" 10% "0"
"1"
OUTn
"0"
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STV7699
INPUT/OUTPUT SCHEMATICS Figure 2 : F/R, BLK, POL, HIZ Figure 3 : CLK, STB
VCC (Pin 100)
VCC (Pin 100)
F/R, BLK, POL, HIZ (Pins 89, 88, 87, 86)
CLK, STB (Pins 95, 94)
VSSLOG (Pins 90 to 93)
7699-04.EPS 7699-05.EPS 7699-07.EPS
VSSSUB (Pins 41-81)
VSSSUB (Pins 41-81)
VSSLOG (Pins 90 to 93)
Figure 4 : Ai, Bi
VCC (Pin 100)
Figure 5 : Power Output
A4 to A1 (Pins 96 to 99) B1 to B4 (Pins 82 to 85)
VPP (Pins 1, 29, 30, 51, 52, 80)
VSSSUB (Pins 41-81)
VSSLOG (Pins 90 to 93)
OUTi (Pins 2 to 5, 7 to 14, 16 to 23, 25 to 28, 31 to 34, 36 to 39, 42 to 45, 47 to 50, 53 to 56, 58 to 65, 67 to 74, 76 to 79) VSSP (Pins 6, 15, 24, 35, 40, 46, 57, 66, 75)
VSSLOG (Pins 90 to 93)
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7699-06.EPS
STV7699
PACKAGE MECHANICAL DATA 100 PINS - PLASTIC QUAD FLAT PACK (PQFP)
A A2 80 e A1 51 0,10 mm .004 inch SEATING PLANE 50
81
100
31
E3 E1 E
B
1
K
Dimensions A A1 A2 B c D D1 D3 e E E1 E3 L L1 K
Min. 0.25 2.55 0.22 0.13 22.95 19.90
Millimeters Typ.
Max. 3.40 3.05 0.38 0.23 23.45 20.10
Min. 0.010 0.100 0.0087 0.005 0.903 0.783
Inches Typ.
Max. 0.134 0.120 0.015 0.009 0.923 0.791
2.80
0.110
16.95 13.90 0.65
0o (Min.), 7o (Max.)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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5F.TBL
23.20 20.00 18.85 0.65 17.20 14.00 12.35 0.80 1.60
17.45 14.10 0.95
0.667 0.547 0.026
0.913 0.787 0.742 0.026 0.677 0.551 0.486 0.031 0.063
0.687 0.555 0.037
PMPQF100.EPS
D3 D1 D
30
c
L1
L

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